Investors

Taking a validated architecture to production silicon and first licences

Backed by Draper Associates since 2017. The capital funds the step from validated array to production tape-out, delivers partner-optimised arrays with tailored memristors as the commercial proof point, and carries existing engagements through qualification. It does not fund the discovery of whether the physics works.

Draper Associates
Backed since 2017

Early institutional backer

2017
Founded

Nine years of deep-tech engineering

Partner-ready
Commercial proof point

Arrays optimised for partner solutions

How the business is built

Two phases, in order. The first funds the second.

CyberSwarm designs neuromorphic computing hardware and licenses it as intellectual property. Revenue arrives in two phases, and they are sized differently.

  1. Phase one

    Hardware, near term

    Modules built on our own arrays, sold into defence, industrial and automotive applications where the power envelope leaves no alternative, alongside engineering fees during co-development. This is specialised hardware, not volume consumer silicon. It produces revenue while the architecture is still being proven at scale, and it puts working systems into customers’ hands, which is what makes the licensing conversation credible later.

  2. Phase two

    Licensing, once the architecture is proven at scale

    The ARM model. Once reference designs exist, two things are licensable: the architecture itself, and the memristor devices, which other manufacturers fabricate under licence. Revenue becomes a per-unit royalty on licensee volume, with no inventory and no fab risk on our side. The relevant denominator stops being our own production capacity and becomes the connected-device base.

The two phases are not alternatives. Hardware revenue during the proving period is what allows the licensing transition to be made from a position of demonstrated deployment rather than from a specification.

Revenue architecture

Four streams, arriving in sequence

StreamTimingCharacterMargin profile
Engineering and co-developmentImmediateMilestone-based; funds integration engineeringCost recovery plus
Hardware supplyNear termFramework agreements, deployment-drivenProduct margin
Licensing royaltiesPost-integrationPer unit, at licensee volumeNear-zero marginal cost
Support and toolchainOngoingAnnual, attached to licencesHigh

The structure is deliberate. Engineering fees and hardware supply generate revenue during the period when royalties cannot yet exist, bridging the qualification-cycle gap. Royalties are the terminal value.

Why licensing rather than manufacturing

The capital scales with engineers, not with wafers

  • No fab capital, no wafer commitments, no inventory risk
  • Capital requirements scale with engineering headcount, not with volume
  • One design win produces a decade of royalties in automotive and defence
  • Licensees own system integration, which no company could staff for across every vertical

Investment thesis

Six reasons this is a different bet from every other AI-chip company

The moat is in the material

Most AI-hardware companies compete on architecture on top of a foundry process anyone can buy. CyberSwarm’s advantage begins one level lower, in a patented IGZO resistive element and the array built from it. That is expensive to replicate and difficult to design around.

The constraint finally binds

For a decade, edge AI was a nice-to-have because models were small enough to fit or workloads could be pushed to a data centre. Physical AI removes both escapes: a robot, a vehicle or an implant has a fixed power budget and no acceptable round-trip. The architecture that wins there is the one that stopped moving weights.

Not a head-on fight

We are not building a training accelerator, and we are not asking anyone to abandon their GPU cluster. We sit at the deployment end of the same pipeline, in devices those clusters will never be installed in, which makes the incumbents distribution partners rather than obstacles.

Silicon alone does not sell

The reason novel hardware fails commercially is almost never the hardware. It is that nobody can deploy to it. Compiler, runtime, calibrated simulator and PyTorch-compatible SDK are built alongside the device precisely so that adoption does not require faith.

Sovereignty is now a purchasing criterion

European defence, industrial and healthcare buyers increasingly need compute that is not dependent on a foreign cloud. An architecture where inference physically cannot leave the device is a strong answer to a question procurement is now required to ask.

Nine years of compounding

Founded 2017, filing since 2018, granted patents in 2024 and 2025. Current funding accelerates the step from validated architecture to production silicon and first licences, not the discovery of whether the physics works.

Market

The demand is not speculative. It is already being bought

Every figure below is published by the analyst house named beside it. We do not model our own market.

$36.2B

Edge AI chip market, 2026

Grand View Research. Projected to $291.8B by 2033, 34.7% CAGR

$20.3B

Neuromorphic computing by 2030

Grand View Research, from $5.3B in 2023, 19.9% CAGR

$96B

Edge AI chipset market, 2031

ABI Research, from $34.4B in 2026

Where we sit in it

Third-party estimates of edge AI silicon vary by an order of magnitude depending on what is counted, which reflects disagreement about definitions rather than about demand. We cite them for orientation and do not rely on any of them.

The denominator that matters to a licensing business is devices, not wafers. The installed base of connected devices passed 18.4 billion units in 2025 and is forecast to exceed 38 billion by 2030. We address the subset that must adapt locally: automotive sensing and ADAS nodes, defence and autonomous platforms, industrial sensing and predictive maintenance, and robotics.

Traction

What exists today

  • Granted US and European patents covering the resistive element, the array and the network built from them, with fourteen applications pending
  • A 4 × 4 module running with its full interface electronics: ~97% accuracy on a standard classification benchmark, ~1 ms inference, 200–350 mW measured
  • Array dimensions are a design choice: arrays are configured and built to the size the implementation calls for
  • A neuromorphic-powered drone demonstration completed for a defence counterparty
  • A paid engineering engagement with a global automaker, currently in the customer’s own testing
  • A hardware-based security product on the same substrate, close to commercialisation
  • Engineering in Bucharest, headquarters in San Mateo, and a compliance posture built for defence-adjacent work

Engagements are described by status, without naming counterparties, and without a weighted pipeline figure. The same record, in more detail, is on the projects page.

Roadmap

Twelve-month execution plan

Eight parallel workstreams, board-approved. Three run today with current headcount; five commence on funding. Together they take the architecture from a validated array to production silicon and the first royalty-bearing agreements.

  1. 01

    Running

    Manifold proof

    The physical manifold proof, in software and electronics hardware. The 4 × 4 module is operational with full interface electronics and software control of array input and output.

  2. 02

    Running

    Integration engineering

    Field application support for co-development partners. Active against the automotive engagement in testing.

  3. 03

    Started

    Toolchain and SDK

    The compiler and model-mapping layer for licensees. The workstream the company names as its genuine execution risk.

  4. 04

    Commences on funding

    Production silicon

    The architecture is developed and validated; this workstream takes it to manufacture. Mask sets, design tooling, IP blocks, test and validation, and the foundry engagement, culminating in tape-out.

  5. 05

    Commences on funding

    Partner-optimised arrays

    Fabrication, characterisation, and commercial proof of concept for different types of arrays with memristors optimised for partners’ solutions. Array fabrication is demonstrated; integration and interconnection with the electronics begin on funding.

  6. 06

    Commences on funding

    US operations

    Entity, staffing, manufacturing readiness, for the initial hardware phase and for defence-adjacent work.

  7. 07

    Commences on funding

    Compliance

    Export-control programme, CFIUS, ITAR posture assessment. ECCN 3E001 classification is complete; the programme commences on funding.

  8. 08

    Commences on funding

    Organisational scaling

    To approximately 51 people, weighted toward device engineering, circuit design, toolchain and field application engineering, and sequenced to remove single points of dependency first.

Post-funding, the roadmap moves from single-array proof to multi-array systems, a productised licensable IP core with full toolchain support, and qualification cycles in automotive and defence.

The commercial proof point

Partner-optimised arrays

The stage at which the architecture transitions from demonstrating physical principles to delivering arrays with memristors tailored to partner specifications. Five milestones lead to it, each with the dependency it waits on.

Array design freeze
Depends on: characterisation complete on the current generation.
Fabrication run
Depends on: foundry slot secured.
Electrical characterisation
Depends on: test infrastructure in place.
Reference workload benchmarking
Depends on: customer-relevant benchmark set agreed.
Commercial proof of concept
Depends on: delivered to the lead integration partner.

The gate is the same in every engagement: a customer-relevant inference workload, executed on arrays optimised for partner solutions at the target power envelope, witnessed by the counterparty. That artefact moves a discussion to co-development, and co-development to a licence. It is what this funding supports.

Competitive landscape

Where we differ, and where we are behind

CategoryApproachWhere we differ
GPU and general acceleratorsDigital, memory and compute separatedWe remove the data-movement energy cost architecturally
Edge NPU and digital ASICDigital, fixed-function, optimised dataflowSame architectural energy floor; we operate below it
Analogue in-memory startupsCrossbar-based, Euclidean representationNon-Euclidean geometry implemented in hardware
IP licensorsDigital cores, mature toolchainsWe compete on a design point they cannot reach; they compete on ecosystem maturity

Where we are behind: toolchain maturity and ecosystem. Established IP licensors have decades of compiler, tooling and developer support. The toolchain workstream addresses this, and it is a genuine execution risk rather than a formality.

Where the moat sits: the combination of granted patents, process trade secrets held outside the filings, export-control compliance capability, and the geometric approach itself. Any one is replicable in time. The combination is not easily.

Risks and mitigations

Stated plainly, with what is done about each

  1. Tape-out execution

    The central near-term risk. Production silicon is the gate everything else passes through.

    What is done

    Foundry partner selected; the largest single allocation of capital; staged validation before mask-set commitment.

  2. Long qualification cycles

    Automotive and defence convert on the customer’s timeline, not ours.

    What is done

    Engineering fees and hardware supply bridge the gap; multiple verticals with independent cycles.

  3. Toolchain maturity

    Behind incumbent IP licensors on developer ecosystem.

    What is done

    A dedicated workstream; early licensees co-develop against real workloads.

  4. Scaling the organisation

    Organisational risk at this growth rate is real, and key-person concentration is a real exposure at current scale.

    What is done

    Sequenced hiring; a two-site structure; documentation and deliberate redundancy in the device and circuit teams.

  5. Manufacturing and yield

    A novel process at commercial scale, in the initial hardware phase.

    What is done

    An established foundry partner; a conservative array scaling path rather than a single large jump.

  6. Export control

    ECCN 3E001. An operating requirement and a screening constraint on counterparties.

    What is done

    A funded compliance programme; counterparty screening; US operational control and domestic hiring intent. It is also a barrier to entry for competitors without a compliance function.

  7. Counterparty concentration

    The pipeline is weighted to a small number of partners.

    What is done

    A non-exclusive channel structure; field-limited licensing prevents foreclosure of a market.

  8. Incumbent competitive response

    Large players can fund parallel research.

    What is done

    Patent position established; process trade secrets undisclosed; the geometric approach is not an obvious adjacency.

Backers

Backed by

Draper Associates

since 2017

Silicon Valley

“Neuromorphic computing is not meant to replace digital systems. It represents a new computational layer between traditional computing and quantum. Designed for problems that neither solves efficiently.”

Mihai Raneti · Founder & CEO, CyberSwarm

Diligence

The questions we get asked first

In two phases. First, hardware: modules built on our own arrays into defence, industrial and automotive applications, plus engineering fees during co-development. Then licensing, ARM-style: the architecture and the memristor devices themselves, fabricated by others under licence, earning a per-unit royalty at licensee volume with no fab or inventory on our side. Support and toolchain revenue attaches to each licence. The first phase funds the second.

Two things changed. Physical AI moved from research demos into products with real power budgets, and the models that need to run at the edge stopped being small enough to brute-force on a microcontroller. The gap between what deployment requires and what conventional architectures deliver is now wide enough that customers will accept an unfamiliar computational model.

Analogue in-memory compute is an active field, including research programmes inside the largest semiconductor companies. Very few groups own the device chemistry, the array architecture and the deployment toolchain together, and fewer still have granted patents with 2018 priority dates. That combination, not the concept, is the differentiator.

Near term, tape-out execution: production silicon is the gate everything else passes through, and it carries the largest allocation of capital. Behind it, two more we state plainly. Toolchain maturity, where established IP licensors have decades of developer support and we do not. And qualification cycles in automotive and defence, which run on the customer’s timeline and are bridged by engineering and hardware revenue until royalties exist.

It is optimised for inference, and we treat that as positioning rather than limitation. Training consolidates into a small number of large facilities; inference disperses into billions of devices. The dispersed side is the larger, more constrained and more defensible market, and it is the one where our advantages bind.

The full data room is available on request.

Investor relations reaches the founding team directly at mihai@cyber-swarm.net.