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Computation that happens in the memory, not next to it

A memristor stores a value as a physical resistance. Arrange millions of them in a grid and the grid performs a matrix multiplication by itself. That is the whole architecture, the rest is engineering.

Our thesis

The architecture participates in computation.

The physical organisation and state of the machine are part of how information is processed, not the container it happens in.

  1. The weight never moves

    Storage and arithmetic happen in the same physical component, so there is nothing to fetch and nothing to write back.

  2. A layer resolves in one step

    Apply a voltage and the array settles to the answer, instead of working through millions of trips to memory to reach the same result.

  3. A material already made at scale

    The thin film behind high-resolution displays, deposited uniformly over large areas at low temperature.

The wall

AI got bigger. The machine underneath it did not change.

Almost every processor in the world is built the same way: memory on one side, arithmetic on the other, and a bus in between. For a neural network, which is mostly one enormous multiply-accumulate, that bus is the whole problem. The energy is not spent computing. It is spent moving weights back and forth.

Moving a number from DRAM into a compute unit costs orders of magnitude more energy than the multiplication it feeds. Scale that to billions of parameters, several hundred times a second, inside a car or a drone or an implant, and the architecture runs out of budget long before the model runs out of accuracy.

The budget, and what moving weights does to it

Model size
1.0M parameters
Moving the weights
39 mW
The multiplication
0.11 mW

Moving the weights fits inside a 1 W budget

A 1 W budgetModel size, in parameters

A first-order model: every weight fetched from DRAM once per inference and multiplied once, thirty inferences a second, no caching. 1.3 nJ per access, the low end of the range, and 3.7 pJ per multiply, from Horowitz, ISSCC 2014.

3.7 pJ

One multiply

32-bit floating point

1.3–2.6 nJ

One DRAM access

The trip that feeds the operation

350–700×

What the trip costs

Per number, every time

The arithmetic is nearly free. The traffic is not, and a neural network is mostly traffic. Figures for a 45 nm process from Mark Horowitz, “Computing’s Energy Problem (and what we can do about it)”, ISSCC 2014.

The way through

Four layers, from the material up

Every other processor treats its hardware as a passive platform for algorithms. Here the electrical state of the array is part of the arithmetic. Neuromorphic, here, is not about reproducing biology. Nature is where the principle was found, not a thing to copy: the useful part is that storage and computation can be the same event.

From the lattice, out to the device

The oxide lattice, and the oxygen in itTwo contacts, in the same planeThe path across the gap, once it forms

The component

A component that remembers what current went through it

So one element has to do two jobs: store a value, and act on a signal passing through it. A memristor does both. It is a two-terminal element whose resistance changes with the charge that has passed through it and stays changed when the power is removed — a stored value and a physical multiplier at the same time. It is the closest thing electronics has to a synapse.

  • Non-volatile: the weight survives power-down, so there is no reload cost at wake-up
  • Analogue: many stable conductance levels per cell, not a single bit
  • Dense: a passive element at the crossing of two wires, with no transistor per weight required
  • CyberSwarm builds its elements from an IGZO resistive layer, programmed and read through planar contacts

The array

The value is stored where the computation happens

Arrange memristors at every intersection of a grid of row and column lines and you get a crossbar. Drive the rows with voltages and each cell passes a current equal to voltage times conductance. Ohm’s law does the multiplication. Every column sums those currents automatically, because that is what Kirchhoff’s law does at a node.

  • A full matrix-vector product resolves in one analogue step, not O(n²) clocked operations
  • Weights never move: there is no fetch, so there is no memory bottleneck to pay for
  • Latency is set by the settling time of the array, not by the size of the layer
  • Energy per operation is set by the physics of the cell, and it is very small
Input voltages VMemristors hold the weights GColumns sum the currents I = Σ V·G

The material

Multiple device families. One array architecture

A memristor is defined by its behaviour, not by one chemistry. CyberSwarm develops several device families; the one documented here is built on IGZO. Indium-gallium-zinc-oxide is the semiconductor behind high-resolution displays, which means it is a material the world already knows how to deposit uniformly over large areas at low temperature. CyberSwarm uses it for both the switching elements and the thin-film transistors that select them, and the resulting array is transparent, so it can sit behind a display rather than beside it.

90
Resistive states

Recorded on a single device

10² Ω – MΩ
Resistance span

A few hundred ohms to megaohms

10×
Reversible tuning

Gradually, within one order of magnitude

Dumitru, Besleaga, Ionescu, “Analog IGZO Memristor With Extended Capabilities”, IEEE Journal of the Electron Devices Society, 2020.

  • Low-temperature deposition, compatible with substrates conventional CMOS cannot use
  • The same layer stack provides the selector transistor and the resistive synapse
  • Programmed by localised thermal treatment through voltage sweeps, giving multiple stable states
  • Read with a low-voltage pulse, which is below the threshold that would disturb the stored state
Current against voltage over twenty-four subsequent positive sweeps on one IGZO device, each to a slightly higher voltage limit. Every sweep traces a narrow loop with a downward hook near its limit, and each starts flatter than the last, so the family fans downward as the limit climbs from about three and a half to about six volts.Subsequent sweeps012345670102030Voltage, VCurrent, mA
After figure 6(a) of the company’s IEEE JEDS paper (2020): subsequent positive sweeps, each to a higher voltage limit. Redrawn to the figure’s proportions, not traced from its data. Each sweep raises the resistance a little near its limit and the device holds the new state, so the family fans downward while the limit climbs.

The architecture

Many small arrays, behaving like a swarm

A large model is not mapped onto one enormous array. It is tiled across many small ones that operate concurrently and exchange only sparse events. Intelligence is distributed across the fabric, so a degraded tile is a local loss of precision rather than a system failure.

  • Tiles compute in parallel and communicate with event-driven sparse traffic
  • Redundant mapping and on-line re-calibration route around stuck or drifted cells
  • Degradation is graceful: accuracy falls off slowly instead of the chip going dark
  • The same fabric scales from a single sensor node to a multi-chip module
ComputingIdle. Near-zero drawDegraded. Routed around

Hardware × mathematics

Different hardware enables different mathematics

A model shaped for a crossbar is not the model you would write for a GPU, and the advantage only appears when the array and the mathematics are designed together. That co-design is the product: an architecture, and the operations it makes cheap.

The same logic runs down to the material and up to learning. How an array computes is a property of how its devices behave together, so the devices are made in the company’s own laboratory rather than sourced; and learning is implemented through spike-timing-dependent plasticity, consistent with the analogue substrate rather than bolted onto it.

It is also where this architecture parts company with the rest of analogue in-memory computing, nearly all of which assumes a Euclidean representation space. Hierarchical and relational data — which is what sensor, scene and graph data actually is — embeds poorly into flat space and takes disproportionate dimensionality to represent faithfully. Non-Euclidean geometry is implemented here at the hardware level, so the representational geometry matches the structure of the data. Commercially that appears as representational efficiency per unit of silicon.

A model, mapped onto the tiles

A layer of the model, being carried acrossA tile, holding the weight it was given

Stated as principles: computation is physical, memory is distributed, dataflow is spatial, and the state that holds a value is programmable.

The path of one layer

From an operator to the array, and the trip that is not made

One layer of a network, followed from mathematics to physics. Pick a station to stop the belt and look at it.

Pick a station on the drawing, or here.

A small chip on a transparent substrate, held at an angle, with a gold-bordered grid of crossbar cells across its face.

The grid you can see is the array itself. Every crossing in it is one cell, and that cell both holds a weight and computes with it, which is why nothing has to travel for the arithmetic to happen.

See the lab it came out of
“We store the same way we process.”

Mihai Raneti · Founder & CEO, CyberSwarm

Measured

What has been measured, on hardware that exists

One standard classification benchmark, two neural networks, the same physical module. Characterisation, not projection.

~97%

Accuracy

Analogue implementation

~82%

Accuracy

Binary implementation, identical substrate

~1 ms

Inference latency

Per inference. Bounded by the interface electronics chosen, not by the array

200–350 mW

Power

Array together with unoptimised test control electronics

The comparison is internal. It isolates the contribution of the context-aware analogue approach against a binary implementation on identical substrate, and it is the basis for the architectural position rather than a claim against conventional processors.

Technology readiness is assessed at TRL 4: the component validated in a laboratory environment, with the full signal path demonstrated end to end. Benchmarking against customer-relevant reference workloads at production scale begins with arrays and memristors tailored to partner requirements. The figures above characterise the substrate and the architectural comparison, not application performance in a deployed system.

What exists today

A 4 × 4 module, running

The fully integrated unit today is the array with its complete interface electronics, with the computational geometry programmable, reconfigurable while it runs, and measurable.

The integrated module
A 4 × 4 module array with their full interface, under software control of input and output. Chosen as the smallest unit that exercises the whole architecture end to end, for engineering and manufacturing tractability rather than as a limit. Modules interconnect and pass energy to adjacent modules.
Testing now
The manifold proof. The geometry can be set, reconfigured while the module is running, and observed. The module is designed to scale rather than to demonstrate, and the path to custom arrays optimised for partners’ solutions runs through it.
Array size
Array dimensions are not fixed by the architecture. Arrays are modified and built to the configuration that best fits the implementation, so the size follows the workload rather than the other way round. Configurations optimised with specific memristor types for partners’ requirements are the commercial target this programme builds towards: they are not fabricated today, and the module described above is what exists.
The device platform
Nine memristor families, and around twenty device types tested and reproducible across them: titanium-based devices, new IGZO formulations, organic and biologically derived materials among them. Each has its own profile of conductance range, switching, retention and operating envelope, which is what lets one architecture reach different environments without a redesign. Suitability for a specific environment is currently inferred from material properties rather than established by qualification testing.
The interface electronics
Built on established analogue parts in current production, chosen for energy conservation and signal handling rather than process modernity, so there is no obsolescence exposure. The way they are applied to a memristor array is proprietary.

The module, as it runs

Sixteen cells hold one programmed geometryA read sweeps the rows; the columns sumCells re-programmed between reads, without stoppingThe result passed to the next module

Side by side

Von Neumann versus in-memory compute

Not a benchmark, a structural comparison. The two architectures spend their energy on different things.

DimensionConventional processorCyberSwarm crossbar
Where computation happensIn an ALU, after the data arrivesIn the memory cell itself
Cost of a matrix-vector productO(n²) clocked MAC operationsOne analogue settling step
Dominant energy costMoving weights across the memory busCell current during the read pulse
Behaviour when idleClocked; leakage continuesContinuous-time analogue computing; no clock to leak against
Weight storageVolatile SRAM/DRAM, reloaded on wakeNon-volatile in the array, instant wake
Failure modeA fault in the datapath is fatalA degraded cell is a local precision loss
Data leaving the deviceTypically offloaded to a cloud acceleratorNever. Inference is local by construction

Security

Security is not a layer on top. It is a property of the architecture.

“You can see only what I give you. I can see only what you give me.”

Every part of the system operates on that one rule. Access is determined by explicit architectural boundaries rather than by depending only on external security mechanisms.

In defence, automotive, industrial and medical systems the requirement has shifted from securing the link to eliminating it. Every transmission is an attack surface and a data-governance event. Local inference converts an unsolvable security problem into a satisfiable design constraint.

The same substrate carries a hardware-based security product, close to commercialisation: a distinct commercial track alongside inference, and the nearest-term one.

Boundaries, not permissions

Given: a packet crosses at the apertureNot given: the boundary holds

Engine

Reference-design characteristics

ParameterValueBasis
Cell technologyIGZO thin-film resistive synapsePatented
SelectorIGZO thin-film transistor, 1T1RPatented
Levels per cellMulti-level analogueReference design
Array organisationTiled crossbars, event-routedReference design
Weight retentionNon-volatile, no refreshArchitectural
Cold-start latencyNo weight reload requiredArchitectural
Host interfaceSPI / I²C / MIPI sensor bridgeReference design
ToolchainPyTorch export, compiler, runtime, simulatorAvailable to partners
Optical propertyTransparent array, display-integrablePatented

Rows marked “reference design” are architectural targets used for partner scoping. What has actually been measured, on the module that exists today, is above under Measured. Characterisation data for a specific configuration is shared under NDA during an evaluation.

A layer, as programmed into a tile

Low GHigh G

Try it yourself

The array mapper

Describe a network layer by layer and watch it fall onto the arrays: how many tiles it takes, at which geometry, how much of the silicon holds a weight, and how the digital machine’s cycles compare with the array’s settlings. Three starting shapes, or your own.

Open the mapper

Intellectual property

The architecture is protected at every layer it is built from

The portfolio does not start at a block diagram. It starts at how a resistive state is written into an IGZO thin film, and runs up through the crossbar array to a neural network whose weights and thresholds are both set in hardware. Full register, each filing linked to its own specification and its legal status checked against the register.

Open the patent register
12
Granted patents
4
Under examination
2018
Earliest priority

Straight answers

The questions engineers actually ask

No. GPUs are extremely good at training large models in a rack with a generous power budget, and that is not the problem we solve. CyberSwarm targets inference at the edge of the physical world. Where the budget is milliwatts, the link is unreliable or absent, and the answer has to arrive before the next control cycle. Most partners train on GPUs and deploy on us.

It is noisy, and we treat that as a design input rather than a defect. Networks are fine-tuned with the device model in the loop, so they learn representations that tolerate programming noise, drift and cell variation. The compiler adds redundancy where a layer is sensitive, and the runtime re-calibrates in the field. The accuracy envelope is characterised per model and reported before deployment. You get a number, not a promise.

Conductance drifts, and the amount depends on the state, the temperature and the age of the cell. The simulator models this explicitly, the runtime measures it per tile, and drift compensation runs against reference cells that are programmed but never used for inference. Where an application demands it, a tile can be re-programmed in place.

They are answers to different questions. Quantum targets problems whose complexity is intractable for classical machines, in a cryogenic rack. We target the opposite end: perception and control, in a moving object, at ambient temperature, on a battery. We describe our architecture as a layer between conventional digital systems and quantum, analogue, physical, and deployable now.

Bring a model. We will tell you if it maps.

An evaluation starts with your workload profiled against our calibrated device simulator, including when the honest answer is that this is not the right architecture for it.

Request an evaluationSee the patent portfolio